1. Field of the Invention
The present invention relates to a Phase/Frequency Detector (PFD), and more particularly, to a PFD with precise phase determination.
2. Description of the Prior Art
Generally, the Phase Locked Loop (PLL) comprises a PFD, a voltage controller, and a Voltage Control Oscillator (VCO). The VCO generates a clock signal according to a voltage VX, and feeds the clock signal back to the PFD. The PFD compares the phase of the fed-back clock signal with the phase of a reference clock signal. If the phase of the reference clock signal is ahead of the phase of the fed-back clock signal, the PFD outputs a rising signal (UP) SUP to the voltage controller for pulling up the voltage VX so as to increase the frequency of the fed-back clock signal. If the phase of the reference clock signal falls behind the phase of the fed-back clock signal, the PFD outputs a falling signal (DOWN) SDN to the voltage controller for pulling down the voltage VX so as to decrease the frequency of the fed-back clock signal.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional PFD 100. As shown in FIG. 1, the PFD comprises two flip-flops 1 and 2, and a NAND gate 3. The flip-flops 1 and 2 receive the reference clock signal CLKREF and the fed-back clock signal CLKFB, respectively, and output the rising signal SUP and the falling signal SDN, respectively. The two input ends of the NAND gate 3 receive the rising signal SUP and the falling signal SDN, respectively, and a reset signal SRESET is generated accordingly in order to reset the flip-flops 1 and 2.
Please refer to FIG. 2. FIG. 2 is a timing diagram illustrating the operation of the PFD 100. As shown in FIG. 2, when the first rising edge EREF1 of the reference clock signal CLKREF inputs to the flip-flop 1, after a delay period TD1, the rising signal SUP is pulled up to be logic “1”; when the first rising edge EFB1 of the fed-back clock signal CLKFB inputs to the flip-flop 2, after the delay period TD1, the falling signal SDN is pulled up to be logic “1”. When both of the signals SUP and SDN are logic “1”, after a delay period TD2, the reset signal SRESET is triggered to reset the flip-flops 1 and 2. The shortest period of the reset signal SRESET is TRESET because of the delay. Consequently, when the phases of the reference clock signal CLKREF and the fed-back clock signal CLKFB are too close, the conventional PFD 100 tends to determine incorrectly. As shown in FIG. 2, the phase of the reference clock signal CLKREF is ahead of the phase of the fed-back clock signal CLKFB. However, since the period of the reset signal SRESET is so long that the second rising edge EREF2 of the reference clock signal CLKREF is ignored, causing that the PFD 100, in the next time, determines the phase of the fed-back clock signal CLKFB is ahead of the reference clock signal CLKREF, which is incorrect. More particularly, in FIG. 2, the phase of the reference clock signal CLKREF is ahead of the fed-back clock signal CLKFB, so that the frequency of the fed-back clock signal CLKFB should be increased. However, it is shown in FIG. 2 that the rising signal SUP, triggered by the rising edge EREF3, has shorter period than the falling signal SDN, triggered by the rising edge EFB2, which is, the voltage VX is pulled down. That means the frequency of the fed-back signal CLKFB is decreased instead. Thus, the conventional PFD 100, is limited by the period of the reset signal SRESET, and tends to lock the phase of the fed-back signal in an incorrect direction.
Please refer to FIG. 3. FIG. 3 is a diagram illustrating the relationship between the phase difference and the output voltage of the PLL utilising the conventional PFD 100. It is assumed that the clock of the reference clock signal CLKREF is T. As shown in FIG. 3, when the phase of the reference clock signal CLKREF is ahead of the fed-back clock signal CLKFB by the range from 0 to (TRESET/T), the output voltage of the voltage controller of the PLL keeps rising and positive. That is, the frequency of the fed-back clock signal CLKFB would be increased. However, when the phase of the reference clock signal CLKREF is ahead of the fed-back clock signal CLKFB by the range from (TRESET/T) to 2π, the output voltage of the voltage controller of the PLL, instead, becomes negative. That is, the frequency of the fed-back clock signal CLKFB would be decreased so that the phase of the fed-back clock signal CLKFB is locked to the incorrect direction. When the phase of the reference clock signal CLKREF falls behind the fed-back clock signal CLKFB by the range from 0 to (−TRESET/T), the output voltage of the voltage controller of the PLL keeps falling and negative. That is, the frequency of the fed-back clock signal CLKFB would be decreased. However, when the phase of the reference clock signal CLKREF falls behind the fed-back clock signal CLKFB by the range from (−TRESET/T) to −2π, the output voltage of the voltage controller of the PLL, instead, becomes positive. That is, the frequency of the fed-back clock signal CLKFB would be increased so that the phase of the fed-back clock signal CLKFB is locked to the incorrect direction.